1. Field of the Invention
The invention generally relates to methods for making filamentary pedestal bipolar transistors and, more particularly, to a laser annealing method for selectively forming an epitaxial collector pedestal region for such transistors.
2. Description of the Prior Art
High performance bipolar transistors are known in which switching speed is greatly improved by the elimination of the extrinsic base-collector junction and the undesired capacitance associated with it. In the absence of base-collector capacitance domination, speed-power characteristics at lower power can be further improved by the reduction of the extrinsic base resistance. Such resistance reduction has been achieved by the provision of a low resistance, contiguous polycrystalline silicon base contacting member.
The foregoing techniques are disclosed in U.S. Pat. No. 3,796,613, issued to I. E. Magdo et al on Mar. 12, 1974, for "Method of Forming Dielectric Isolation For High Density Pedestal Semiconductor Devices" and assigned to the present assignee.
It is further advantageous that all of the foregoing considerations be accomplished in a manner permitting narrowing of the intrinsic collector junction so as to maximize device performance and density in integrated circuit chips. According to the technique disclosed in the aforementioned patent, silicon is deposited through an oxide layer which is apertured over the intrinsic collector region. Epitaxial growth results only in the exposed, recessed collector region, as desired, provided that the oxide window delineating said region is at least a certain size so that "bridging" can not occur. Although, ideally, no silicon should deposit on the raised oxide surrounding the collector region aperture, there remains a tendency to do so unless critical silicon deposition conditions are maintained reliably. Any undesired polycrystalline silicon deposits on the surrounding oxide tend to "bridge" over the aperture, preventing desired deposition within the aperture, especially where the aperture is made small for high component density.
In copending patent application Ser. No. 080,648, filed in the names of Anantha et al on Oct. 1, 1979 for "Selective Epitaxy Method For Making Filamentary Pedestal Transistor" and assigned to the present assignee, a method is disclosed for making a filamentary pedestal transistor in which minimum base-collector capacitance is achieved along with reduced extrinsic base resistance for high performance in a manner compatible with reduced device area for high component density. The method comprises depositing silicon on a coplanar oxide-silicon surface in which only the top silicon surface of a buried collector pedestal is exposed through the oxide. Epitaxial silicon deposits only over the exposed pedestal surface while polycrystalline silicon deposits over the contiguous oxide surface. The simultaneous epitaxial and polycrystalline silicon deposition over a coplanar surface inhibits bridging of the exposed pedestal surface by the polycrystalline silicon and allows the polycrystalline silicon to be used advantageously as a low resistance base contact.
Although the tendency of the deposited silicon to bridge over the collector region is substantially reduced in the coplanar deposition method of the cited application, relative to the non-coplanar deposition method of the cited patent, there still is a tendency for the deposited silicon to remain undesirably polycrystalline over the collector region as the collector region continues to be narrowed in size in an effort to achieve even higher orders of device density.